Timing circuits are needed for most memory arrays. However, they are generally very complex and inflexible. Additionally, most timing circuits utilize many extra logic circuits in order to guarantee the cycle time is truly chopped and adjusted to the proper width. It is not uncommon for six or seven stages of logic gates to surround a delay cell with the result that the delay contributed by the simulation and testing of the logic will not necessarily track the actual delay. The reason for this is that it is very expensive and time-consuming to adjust/add circuits/cells after manufacturing prototyping is done. Therefore, it is imperative to have accurate timing designed in during the preliminary stages of manufacturing.
Accordingly, internal clock pulse width is therefore de-facto generally fixed by design and cannot be "tuned". A pulse with tuning is highly desirable or necessary for a variety of reasons including precise on chip monitoring of array performance or clock pulse width adjustment in the early design phase so that one pass design can be more readily obtained.
A number of circuits have been designed to track timing. Some schemes can be found in, for example, U.S. Pat. No. 4,574,204 "Circuit for Holding a Pulse During a Predetermined Time Interval and an Improved Monostable Multivibrator" issued Mar. 4, 1986 to Bonnet; U.S. Pat. No. 4,425,514 "Fixed Pulse Width, Fast Recovery 1-Shot Pulse Generator" issued Jan. 10, 1984 to Orr et al.; U.S. Pat. No. 4,277,697 "Duty Cycle Control Apparatus" issued Jul. 7, 1981 to Hall et al.; U.S. Pat. No. 4,015,145 "Voltage Compensated Timing Circuit" issued Mar. 29, 1977 to Stewart; U.S. Pat. No. 3,532,993 "Valuable Period, Plural Input, Set-Reset 1-Shot Circuit" issued Oct. 6, 1970 to Kennedy; U.S. Pat. No. 3,484,624 "One-Shot Pulse Generator Circuit for Generating a Variable Pulse Width" issued Dec. 16, 1969 to Rasiel et al.; U.S. Pat. No. 3,187,201 "One-Shot Latch" issued Jun. 1, 1965 to Eastman et al.; U.S. Pat. No. 3,073,972 "Pulse Timing Circuit" issued Jan. 15, 1963 and U.S. Pat. No. 3,048,708 "Pulse Timing Control Circuit" issued Aug. 7, 1962.
However, as previously mentioned, all of these designs have at least one or more undesirable attributes in that they are not adjustable, or are imprecise (particularly so in the nanosecond time frame), use up large amounts of power, space and/or require additional adjacent circuits in order to be utilized.
Accordingly, it is an object of the present invention to produce a timer for memory arrays which does not require additional circuitry.
It is yet another object of the present invention to produce a timer for memory arrays which is utilizable for on chip timing measurements with accuracy much better than those of common wafer testers, which tester accuracy is about .+-.0.5 nano-seconds.
It is another object of the present invention to produce a timer which will generate a clock pulse which can be easily adjusted during the on-going design process and hence allow for one pass design.
It is yet another object of the present invention to produce a pulse generator for use in memory circuits including at least one pair of cross-coupled transistors configured as a latch and including a receiver circuit response to the rising edge of an external clock signal for initiating a pulse, a delay circuit connected to the receiver circuit and including at least one of the pairs of cross-coupled transistors, wherein the delay circuit is responsive to the rising edge of the external clock for initiating the switching of the state of the transistor, whereby the delay circuit operates to terminate the pulse when the state of the transistor is changed by a predetermined amount and whereby the width of the pulse is related to the switching time of the pair of cross-coupled transistors.